Poster · Sydney
VeriScope: Measuring Verification-Ready Verilog Artifacts
- When
- Wed 9 Dec 2026, 17:00–20:00 AEDT
- Where
- Hall 1-4, ICC Sydney
Exhibition Centre, Level 1 - Session
- Sydney Poster Session 4
- Authors
- Wei Zhang, Jian Yang, jiajun wu, Junhang Cheng, Chufan He, Yihang Lou, Xianglong Liu
- Organisations
- IQuest, Beihang University, Shanghai Jiao Tong University, Huawei, Tsinghua University
- QRS classification
- Language models