Poster · Sydney
HierSVA: A Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification
- When
- Tue 8 Dec 2026, 10:00–13:00 AEDT
- Where
- Hall 1-4, ICC Sydney
Exhibition Centre, Level 1 - Session
- Sydney Poster Session 1
- Authors
- Maohua Nie, Jiang Zhu, Jingqun Zhang, Zhichen Zeng, Jiayi Wang, Sibo Zhang, Jialin Wang, C-J R Shi
- Organisations
- University of Washington, AMD, RadixArk, UW
- QRS classification
- Agentic AI, Language models, Efficient and distributed ML systems